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[Insights] Evolving Role of Emerging Memories in Next-Generation Computing

Soogil KimSoogil Kim

The semiconductor industry, which crossed successive growth inflection points driven by PC proliferation, the smartphone revolution, and hyperscale cloud build-out, is now on a trajectory toward a $1 trillion total addressable market by 2030, propelled by the rapid commoditization of generative AI workloads. This next computing era demands ultra-low-power operation, high-throughput interconnect, and pervasive on-device intelligence simultaneously across the full compute hierarchy — from hyperscale data centers to autonomous vehicles and wearables — repositioning semiconductor memory from a passive storage medium to an active, workload-aware functional element co-integrated within the compute architecture.


The canonical memory technology triad of Cost (≈ Capacity), Performance, and Power remains the inviolable framework — unchanged throughout the entire evolution of memory technologies. On the DRAM side, the physical limits of 2D planar cell scaling are being overcome through Vertical Gate (4F²) architectures and fully 3D-stacked DRAM, separating cell arrays from peripheral circuits via wafer-to-wafer hybrid bonding to decouple thermal budgets. NAND flash has similarly adopted hybrid bonding as its next technology platform, achieving Cell/Peri thermal history separation, direct wordline/bitline connectivity, and accelerated fab learning cycles. In the AI accelerator domain, HBM (TSV-based die stacking) alleviates the von Neumann memory wall for GPU and NPU tiles. PIM embeds MAC units at the DRAM bank level to cut off-die data movement energy. CXL enables coherent memory pooling at rack scale, while HBF stacks 3D NAND dies in a TSV-based package to serve the KV-cache and model-weight storage tier with NAND capacity economics and HBM-class delivery bandwidth.


Filling performance-density gaps that neither DRAM nor NAND can economically address, a spectrum of emerging NVM technologies is advancing toward production readiness. Chalcogenide-based SOM (Selector-Only Memory) has reached a 16 nm, 2-Deck integration density in 2025, with a Vertical SOM roadmap targeting further scaling via ALD-enabled thin-film deposition. STT-MRAM has demonstrated a 64 Gb 1S-1MTJ test chip at 20.5 nm half-pitch with a 4F² cell footprint; SOT-MRAM and VCMA switching offer complementary paths to higher endurance and lower write energy, though MTJ patterning at near-DRAM half-pitch remains the key commercialization barrier. HfO₂-based ferroelectric memory — 1T1F FeRAM, FeFET, XP-FTJ, and 3D Fe-NAND — demonstrated the world's first 1X nm, 8 Gb FeRAM with a 5 nm HZO capacitor (IEDM 2021), validating sub-1 V operation within a DRAM-compatible process flow across memory-type and storage-type design spaces. Analog Compute-in-Memory (ACiM) performs MAC operations in the analog domain via resistive switching synaptic cells in a crossbar topology, achieving a simulated 95% area reduction and 5.2× power efficiency gain over digital MAC, requiring cross-layer co-optimization across device, circuit, architecture, and algorithm layers.


The full potential of these technologies is unlocked through Heterogeneous Integration, enabling co-packaging across pitch densities from chip-to-chip bump bonding (1~104/mm2) through 3D SoC stacking (105~108/mm2) to monolithic 3D device-level stacking (>108/mm2), progressively dissolving the memory-logic boundary and culminating in workload-optimized systems where Processor, SRAM, DRAM, emerging NVM, and ACiM macros are vertically co-integrated to minimize data-movement energy and maximize memory bandwidth per watt. SK hynix pursues this through an End-to-End R&D framework spanning Physics through Workload — simultaneously building a memory-centric ecosystem and applying system-centric workload analysis to identify high-value architecture targets. Capacity, Performance, and Power remain the inviolable necessary conditions; the sufficient condition for sustained differentiation in the AI era is concurrently delivering scaling, new-tier exploratory, and convergence value — the strategic essence of Memory Customizing, Converging, and Transforming.

 



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