Evolutionary Memory

DRAM has evolved as a volatile memory for high-speed data processing since its concept was proposed in 1966. Starting with the development of 64k DRAM in 1985, SK hynix has led the industry through DDR, LPDDR, GDDR, and HBM, the core technology of the AI era, and established the world's first mass production system for HBM4 in 2025.

Meanwhile, NAND Flash is an innovative technology introduced in the 1980s as a non-volatile memory, enabling massive storage beyond the limitations of magnetic disks. SK hynix began developing 3D NAND in the early 2000s, and entering the 2020s, responded to demand for high-capacity storage driven by AI, cloud, and autonomous driving by expanding to NAND layer counts and commercializing QLC/PLC technologies, initiating mass production of the industry's first 321-layer QLC NAND in 2025.

DRAM memory chip with circuit patterns

DRAM

DRAM is a volatile memory with a 1T1C cell structure, playing a core role in computing by enabling high-speed and large-capacity data input/output in close proximity to CPUs and GPUs. Although its speed is about one order slower than SRAM and it is several times more expensive than NAND, it possesses capacity levels of several GBs and speed characteristics of several Gbps, while maintaining appropriate power and cost competitiveness. Consequently, its application areas are expanding not only in product groups such as computing, mobile, graphics, and consumer electronics but also in the AI field.

The DRAM business model has been sustained for decades through the scaling of cell size and chip size. From a design perspective, improvements in interface performance and innovations in architecture technology have driven product diversification. Furthermore, HBM products have emerged as the core memory of the AI era as a result of applying advanced process technologies and post-process technologies (e.g., TSV, wafer bonding).

Recently, to overcome the limitations of current tech nodes, various tech platform options such as the vertical gate cell scheme, chiplets concept, and 3D cell stacking structure are being proposed.
NAND flash memory wafer with circuit patternsNAND flash memory wafer with circuit patterns

HBM

HBM4: Stacked for Top Performance, Built to Break AI Limit
HBM4 is the most advanced AI memory ever developed, incorporating the highest number of cutting-edge technologies. Its new architecture expands I/O to 2K, enabling a remarkable over 2.8TB/s of bandwidth. By adopting a logic foundry process, it achieves approximately 40% improvement in power efficiency. Furthermore, with advanced packaging technology -Advanced MR-MUF- it realizes up to 16-high stacking, setting a new standard in performance and integration for AI memory.
Significant Bandwidth Increase with New Architecture and 2K I/O
HBM4 introduces a revolutionary architectural change, offering a remarkable memory bandwidth of over 2.8TB/s, powered by its 2K I/O. This advancement enables seamless multi-processing capabilities, specifically optimizing the performance of AI chips for next-level computational efficiency.
Dramatic power improvement by optimized logic foundry process
SK hynix provides a low power memory solution using logic foundry process base die with over than 40% power efficiency improvement.
Leading edge PKG solution enables 16Hi and more
SK hynix has developed the industry's first 16Hi HBM product using its industry-proven advanced stacking technology, Advanced MR-MUF. This breakthrough delivers the highest-capacity memory solution to date, significantly accelerating both AI training and inference performance.
NAND flas  h memory wafer with circuit patterns

NAND

NAND has high-capacity storage as its key characteristic; although it is slower than DRAM, it plays a core role in the storage device market due to its non-volatility, low cost, and high density. In particular, it has established itself as an essential storage device for mobile devices, PCs, and data centers, and in the era of AI and big data, it continues to expand its application areas through high-speed interfaces and low power technologies.

The NAND business model has maintained sustainability for decades through cell density and 3D stacking technologies. Enhancements in interface performance and innovations in architecture (e.g., NVMe, PCIe 5.0) have led to product diversification, while the securing of high speed and high density through advanced process technologies (e.g., Charge Trap, PUC) has positioned NAND as a core storage memory for the AI era.

For 3D NAND technology, research on new structures and materials is underway to overcome physical stacking limits, and next-generation cell and process technologies such as hybrid bonding and FeNAND are also being developed in parallel for high-performance product development.

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