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Heterogeneous Integration Package Technology

Heterogeneous Integration Package Technology is a next-generation semiconductor packaging technology that integrates various semiconductor dies or chiplets with different functions, process nodes, sizes, materials, and performance characteristics into a single package. At the core lies new and technical limitations of fine-pitch scaling intensity, the importance of heterogeneous integration—connecting functionally optimized chiplets at the package level with high density—is rapidly growing compared to the traditional approach of integrating all functions into a single monolithic SoC.
This research area encompasses 2.5D package platforms, 3D package platforms, chiplet architecture, die-to-die interfaces, and high-density redistribution layers (RDL). The ultimate goal is to implement a next-generation system package platform that simultaneously satisfies high performance, low power consumption, high yield, and high scalability.
Particularly in high-performance computing systems such as AI accelerators, HPC processors, high-end GPUs, network processors, and edge AI devices, computational performance, memory bandwidth, power efficiency, and I/O scalability have emerged as key competitive factors. Consequently, heterogeneous integration packages are establishing themselves as the core technology platform determining system performance.

2.5D Package Platform

A 2.5D package is a structure where multiple dies or chiplets are placed horizontally on a silicon, organic, or glass interposer, or an embedded silicon bridge, providing high-speed connections between dies through high-density wiring. This technology is widely used in high-performance GPUs, AI accelerators, HPC processors, and data center processors, playing a critical role especially in implementing ultra-high-bandwidth connections between logic dies and HBM.

The key research direction are as follows:

  • Research on high-density routing architecture based on silicon interposers
  • Research on embedded silicon bridge structures
  • Optimization of high-bandwidth connections between HBM and logic dies

3D Package Platform

A 3D package is a structure that stacks multiple dies vertically and implements inter-die connections using vertical interconnect technologies such as TSVs, micro-bumps, and hybrid bonding. Compared to 2.5D packages, 3D packages can significantly reduce interconnect length, offering superior advantages in bandwidth, latency, and energy efficiency. In particular, high-performance and low-power systems can be realized through memory-on-logic, logic-on-logic, and cache-on-logic architectures—however, due to the structural nature of vertical die stacking, 3D packages face significant technical challenges in heat dissipation, testing, yield, manufacturability, power delivery, and mechanical reliability. Therefore, 3D integration technology requires simultaneous optimization of structural design, process technology, thermal management, reliability evaluation, and cost strategies.

The key research direction are as follows:

  • Research on memory-on-logic 3D stacking
  • Research on homogenous 3D integration based on hybrid bonding
  • Research on face-to-face and face-to-back bonding architectures
  • Research on thermal-aware 3D floorplanning

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