Next Generation Materials

Memory technology is moving past the limits of two-dimensional scaling and into the vertical dimension: DRAM is building upward and NAND continues pushing toward ever-higher stacks, and amid the AI-driven demand for high-performance memory, the importance of wafer-level-package (WLP) materials has grown substantially in securing HBM device performance and reliability. The vertical era pushes aspect ratios to extremes and in the packaging domain it demands far more precise planarization. To meet the performance that devices demand, material innovation of an entirely new concept and even more precise control are required. Realizing ultra-fine patterning and three-dimensional structures now hinges on material technology that tunes the chemical and physical properties of key process materials at the molecular scale. EUV materials for ultra-fine patterning require development of new photoresist chemistries to overcome the increasingly tight RLS trade-off. Etch gases hold the profile fidelity of high-aspect-ratio patterns, precursors drive uniform films and defect suppression, chemicals and CMP slurries set planarization precision, and wafers anchor the substrate yield that everything else builds on. When molecular-scale design and ultra-high-purity purification deliver angstrom-scale control, competitiveness in next-generation semiconductor manufacturing moves beyond a reliance on equipment performance alone and into a structure where material technology holds the lead. Our research converges over one direction — total material solutions that span patterning, chemicals, CMP, etch gases, precursors, and wafers, turning each of these challenges into the next generation of memory and storage.

Patterning Materials - EUV Total Solution

• Toward shorter wavelengths, higher NA, and multi-patterning, we develop a complete EUV material stack that overcomes the resolution-LER-sensitivity (RLS) trade-off while maximizing productivity.
• CAR: low-LUMO polymers optimized with high-absorption PAGs to advance chemically amplified resists.
• MOR: a new approach built on multi-ligand design and high-EUV-absorption metal cores.
• Pattern-assist: pattern-expansion materials and underlayers controlling secondary-electron and H⁺ donation.
• Overcome resolution limits, we develop next level materials: molecular-level resists & spin-on metal hard mask

Chemical Materials - Precision Wet-Etch Chemistry

• As DRAM and NAND stack up, key etch steps shift from dry to wet: metal-recess control and top-to-bottom uniformity across extreme aspect ratios are now the core of etch technology.
• Maximized etch selectivity that removes only the intended film deep inside high-aspect-ratio structures.
• Etch-rate-controllable raw materials balancing etch-enhancing and etch-inhibiting functions for uniform removal.
• Etch by-product solubility enhancement : Materials that maximize the solubility of by-products generated during wet etching to ensure yield and integrity.

CMP Materials - Ultra-High Planarization & Defect controllability

• Pitch-down and stack-up multiply CMP steps and make extreme defect control a core process technology: slurry and pad are co-optimized as one total solution.
• UHPS transition: abrasive engineering with sub-60 nm colloidal silica and sub-100 nm ceria particles.
• Charge-controlling additives for stable abrasive dispersion and minimal defectivity.
• Pad groove material and shape optimization, building a total slurry + pad line-up covering diverse substrates.

Etch Materials - Etch force control to maximize Aspect Ratio

• Development of an etch gas in which, as part of understanding process physics, gas enters, plasma forms, etching behavior occurs, and chemical reactions proceed smoothly.
• Development of gas with enhanced cleaning efficiency by understanding the dry etching process and by gas flux/atomic ratio
• Physical etching by ion collision as part of the selectivity control mechanism for HARC etch. Prevention of lateral erosion outside the downward vertical ion collision zone for sidewall protection, enabling a perfect vertically isotropic profile; and scavenging effect of the hydrogenation gas
• Low GWP Gas, Cryo Etch Gas Devolope & E/R, Selectivity, Cleaning Efficiency, Particle Control.

Diffusion Materials - Next-Generation Material Development and Atomic-Stratum-Size Micro-Deposition

• Enhancing thin-film properties through atomic-layer-scale ultra-fine deposition based on the single-type & ALD furnace process
• Development of materials for increasing capacitance and preventing electrode oxidation through the design of optimal combinations of reactants and precursors for high-k oxides
• Early Identification of Novel Materials to Secure the Operational Characteristics of the ICL (Interface Control Layer)
• Optimization of process performance customization and material design capabilities for SIN, SiO, Poly, and Mo implementations
• Material Properties(TGA/DSC/NMR Assay/ Viscosity/Vapor Pressure) & Film Quality(ALD Window, D/R & Unif), Step Coverage, Gap Fill, Loading Effect) & Electrical Performance

Thinfilm Materials- Next-Generation Metal Development and Improvement of Deposition Uniformity

• Improving thin-film performance efficiency through adhesion control of single-element units based on CVD and sputtering in single-type equipment, and minimizing impurities
• Elaboration of the material adhesion principles by sub-board and the adhesion/release mechanisms according to surface conditions
• Surface modification and adsorption efficiency doubling for the refinement of BDE (Bond Dissociation Energy) control, and improving thin-film quality through precise ligand exchange
• Optimization of impurity control through refinement of precursor design and material ligand design for new metal materials, and enhancement of step coverage and gap fill characteristics
• Development of customizable materials with resistance, D/R, S/C, G/F, and Film density.

Wafer Materials - Circuit board material that withstands extremes through defect control

• It refers to a single-crystal silicon thin film that serves as the substrate for manufacturing semiconductor chips, and its key quality characteristics include flatness, surface defects, crystal defects, and wafer edge & notch dimensions
• Wafers are classified by size (200 mm, 300 mm), dopant type (N-type, P-type), crystal orientation, and notch position (100, 110, 111), additional processing (polished wafer, epitaxial wafer, SOI wafer), and material (SiC, GaN, SiCOI, GaNOI)
• The wafer manufacturing process is Growing→Cropping & Slicing→Edge Grinding→Lapping & Grinding→Double Side Grinding & Etching → Double Side Polishing & Re-Polishing → Flatness Insp→Final Cleaning →Particle Counting→Epi Growing→Packing

WLP Materials (Wafer Level Package) - Materials package for AI Memory

• Toward next-generation HBM and advanced 2.5D/3D packages, WLP materials serve more process steps under ever-more-severe requirements we optimize front-end materials for package processes and develop WLP-dedicated systems.
• Hybrid-bonding HBM: the shift from gap-height shrink to zero gap makes wafer flatness the core technology.
• Cu CMP slurry optimization and cleaning solutions delivering bond-ready, atomically flat surfaces.
• Next-generation dielectrics for CoWoS-class devices and ultra-high-aspect-ratio patterning materials for advanced integration.