Revolutionary Memory
Our core vision is to innovate memory to create a better and sustainable world. Our revolutionary memory research aims to push memory technologies further than ever imagined. Our vision serves as the backbone of SK hynix’s memory roadmap, specifically designed to defy the scaling limits of DRAM and NAND technologies by adopting innovative materials, processes, structures, and products. In addition, new memory technologies, which break the existing frames, will present a new path forward for memory. At SK hynix, we are striding forward with future DRAM, future NAND, and new memory devices to shift the paradigm of memory in the semiconductor industry.

Future DRAM
- FRAM(Ferroelectric RAM) is non-volatile random access memory with DRAM-level speed. World-first 1Xnm half-pitch FE-RAM with 8Gb density was fabricated, and operation was confirmed. We showed that FRAM operation is possible even at low operating voltage using 2Pr from pinched hysteresis of the 5nm- thick ultra-thin HZO capacitor. We confirmed that FRAM cells operate at write time under 80ns and speed characteristics can be improved by Vcore optimization.
- The InGaZnO channel is attracting attention to improve the refresh characteristics of DRAM. InGaZnO thin film transistors have been used in the display industry for a long time due to their moderate carrier mobility, extremely low leakage current and substrate size scalability. It can be a candidate for a stackable channel material for future DRAM.

SOCAMM2 (Small Outline Compression Attached Memory Module)
Our SOCAMM2 memory solution based on LPDDR, a proven technology to reduce power in mobile application, provides less power consumption and more capacity per module comparing to RDIMM.

Future NAND
- Our research addresses such hurdles by exploring stack height scaling, new materials, and new 3D NAND cell architectures.
- Examples include applying ferroelectric material to the conventional 3D NAND architecture. We demonstrated the multi-level capable 3D Ferroelectric NAND device using conventional 3D NAND fabrication process, which was published in IMW 2022. Details can be found here. (https://doi.org/10.1109/IMW52921.2022.9779278)
Want to learn more about how we can create new values for semiconductor industry? Please contact us!
We are in this together! Contact Us![[Summary] Co-Optimizing Cell, Non-Cell, and Page Schemes for Energy Efficient Analog Computing in 3D FeNAND](https://mis-prod-koce-research-user-cdn-01-blob-ep.azureedge.net/web/blog/20251231/thumb_y5dtflR7.20251231154647949.png)
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![[Summary] 224 TOPS/W-level Analog Computation in Memory Cell Using Hybrid Ferroelectric Tunnel Junction Having Enhanced On-State Conductance](https://mis-prod-koce-research-user-cdn-01-blob-ep.azureedge.net/web/blog/20250716/thumb_qYH3UUzv.20250716094321913.png)