This study presents cell design parameters to be considered for a two-terminal ovonic threshold switch (OTS) and phase-change memory (PCM)-based array, with an example of 3-D cross-point array (XPA). The 1-Mb 3-D XPA in this study was simulated using MATLAB. The array characteristics were analyzed using the Monte–Carlo simulation for the variability of OTS characteristics. We observed that the OTS threshold voltage ( Vth ) variation further accelerates the IR drop, increasing Vth of cells in real XPAs. This further reduces the read window margin (RWM) and inhibit-fail margin (IFM), creating constraints on 1-Mb normal operation. The IR drop is more significant at RESET (RST) than the selected cell is at SET. Furthermore, the higher the RST resistance ( Rrst ), the more severe it is, increasing the inhibit bias and worsening inhibit fails. Based on the simulation results, the raw bit error rate (RBER) of the 3-D XPA device can be minimized by balancing Rrst of the PCM to minimize the error bits between failures from insufficient RWMs and inhibit fails, as the two errors are directly related to Rrst . Finally, we show that the 3-D XPA device can be fabricated when Rrst of the memory material is sufficiently large to minimize failures from insufficient RWM, and Vth (OTS Vth ) of the selector material is adjustable to Rrst to minimize inhibit fails.