R&D Division at SK hynix will introduce 4F2 DRAM with a peri-under-cell (PUC) architecture as a next-generation DRAM platform at 2026 IEEE/JSAP Symposium on VLSI Technology & Circuits to be held in Honolulu, Hawaii June 14-18 2026.

[Electrical Characteristics of the 4F2 Vertical Gate (VG) DRAM integrated with Bit-Line Shielding (BLS) and Back Gate (BG) Transistor/Joodong Park]

This paper will present the electrical characteristics of 4F2 vertical gate (VG) DRAM such as data retention and sensing capability. The proposed VG DRAM incorporates key technologies including bit-line shielding (BLS) to suppress coupling noise and shared back gate (BG) structure to enhance threshold voltage (Vth) control and passing gate effect. Die-thinning technology will also be introduced to support reliable circuit operation in wafer-bonded structure. Results demonstrate the feasibility of 4F2 VG DRAM architecture providing a viable development path toward competitive future DRAM products.