Up to now, there has been a lot of research done on developing emerging memories to make an effective bridge between CPU/DRAM and SSD from the perspective of the memory hierarchy, considering cost, performance, and other factors.

CXL (compute express link), a new class of interfacial protocol, has emerged, and memory tiers are suggested for optimizing performance and capacity at each workload. Particularly for persistency expansion and capacity expansion, 3D CPM (cross-point memory) has attracted attention as a gap-filler between DRAM and storage.

Fig. 1 (Left) Cross section TEM of 4-deck cell array with Cu multi-layer and PUC (Right) Floor plan of 20nm 4deck 256Gb chip

We shared the result of 2-deck 64Mb test chip operation with 2z nm in 2018 IEDM and successfully demonstrated a 128G chip in 2019. In 2023 VLSI, we demonstrated progress on 4-deck 256Gb chip operation with 20nm technology. 

Fig. 2 (left) Vt distribution of each deck after set and reset operation (right) Basic die information, including structure and operation properties

We developed novel integration schemes including new self-align etching, cleaning, CMP (chemical mechanical polishing), and ILD (interlayer dielectric) deposition. In order to flow enough write current while minimizing spike current, low resistance conductor material was carefully designed for the interconnection scheme. A large read window margin and a tight Vt distribution of the 1Gb array for each deck from 1-deck to 4-deck were achieved by carefully controlling the 20nm pillar patterning process, material design, and appropriate write/ read operation.

Even though we successfully demonstrated 4-deck 256Gb device, we revisited the scalability of CPM beyond 20nm technology.

Fig. 3 Scaling challenges of CPM: (left) Aspect ratio (mid) Set program margin (right) Thermal disturbance

First, CPM (PCM + OTS) structure will have a much higher aspect ratio at shrunken tech and this will lead to complex progress integration. Second, CPM will have a smaller write program margin between set and reset operations as the technology node shrinks. Third, the scaling limit by thermal disturbance is expected to occur at technology nodes beyond 1y nm without the elusive thermal conductivity of inter-layer dielectric.

Therefore, we are preparing SOM (selector-only memory) as an alternative solution for the next generation. SOM is composed of only two electrodes and a single dual-functional material, which can function as a material for both memory and selector. SOM has advantages over CPM in terms of low write latency and low cell power consumption because SOM can eliminate a long crystallization time of set operation and a high reset current of CPM.

Fig. 4 Memory requirement relationship between performance and cost

Finally, we could suggest that the SOM will be a strong solution for next-generation applications with scaling longevity beyond 1znm technology.

The publication: Link