DRAM has been evolving in cell architecture to improve its density, speed, and power characteristics. Conventional DRAM cell transistor based on buried-gate structure faces fundamental scaling limits due to increased process complexity and degradation of device performance in the range of sub-10nm technology nodes. To overcome these challenges, 4F2 VG DRAM has emerged as a promising solution to extend DRAM scaling beyond current scaling limits. In this report, electrical characteristics of 4F2 VG DRAM are reviewed with key integration features such as bit-line shielding (BLS) and back-gate (BG) structures.

Fig. 1 shows illustrated concept and fabricated 4F2 DRAM structure with peri-under-cell (PUC) architecture where VG cell transistor and peripheral devices are connected through fusion wafer bonding and inter-wafer contact process techniques. This integration scheme enables accurate electrical characterization of VG cell transistor as well as functional verification of product-level operation.

Fig. 1 Structure of 4F2 DRAM with peri-under-cell (PUC) architecture

Back gate (BG) integrated in VG cell transistors enables Vth modulation and suppresses electric field interference induced by biasing of adjacent word-lines (WLs). Fig. 2 shows structures of VG cell transistor with and without BG implementation. As shown in TEM images, BG is positioned between two WL pillars and is shared between the neighboring cells without increasing unit cell size. 

Fig. 2 Structure of Shared Back Gate (BG)

As shown in Fig. 3, shared BG improved threshold voltage modulation by applying a back-bias and it suppresses the electric field coupling from adjacent word line biasing, improving electrostatic integrity of the cell transistor. BG also introduces trade-offs of cell transistor performance such as degradation of on-current and sub-threshold swing.

Fig. 3 Back Gate (BG) Effect on Cell Functionality

In VG cell architecture, parasitic capacitance in between bit-lines increases drastically as a consequence of the compact VG layout where BLs are routed vertically in close proximity. To address this issue, structural solution for elevated sensing noise was proposed. Fig 4 shows conceptual design of bit-line shielding (BLS) circuit and TEM images of BLS structure employed in this work.

Fig. 4 Bit-line Shielding (BLS) Structure

BLS structure implemented between adjacent BLs substantially reduces effective BL-to-BL coupling noise, resulting in enhancement of sensing capability and significant reduction in sensing failures, as demonstrated in Fig. 5.

Fig. 5 Sensing Performance of 4F2 VG DRAM with BLS

In summary, 4F2 VG DRAM array in PUC architecture is successfully demonstrated as a promising candidate for future high-density memory applications. Robust performance of cell transistor and read-write operation of 4F2 VG DRAM is successfully achieved. Effect of shared BG in between adjacent two WLs was systematically evaluated to optimize device characteristics and cell functionality. In addition, feasibility and performance benefits of BLS was verified with effective suppression of inter-BL coupling noise.