The R&D Technology Development Division at SK hynix Inc. will present two technical papers at the 2025 International Electron Devices Meeting (IEDM), taking place from December 6–10 in San Francisco, USA. Demonstrating industry‑leading innovations in next‑generation memory technologies, the company will unveil two key advancements: one addressing the critical challenge of CTN (charge trap nitride) isolation in ultra‑high‑layer 3D NAND, and another introducing a groundbreaking FeNAND architecture designed to redefine performance and energy efficiency for future memory systems.

[A Highly Scalable Isolated Charge Trap Nitride Layer Implemented in a 176 layer 3D NAND Flash with Superior Threshold Voltage Distribution and Charge Retention / Sang-wan Jin]

This paper will present a groundbreaking CTN isolation technology — the world’s first to be implemented in a commercially mass-produced 176-layer 3D NAND device, moving far beyond conventional test vehicle evaluations. This innovation dramatically reduces inter-cell interference and data retention at high stacking levels. Designed for immediate integration into high-volume manufacturing, the technology removes a critical bottleneck in 3D NAND scaling and accelerates the commercialization of next-generation 3D NAND applications. 

[Co-Optimizing Cell, Non-Cell, and Page Schemes for Energy Efficient Analog Computing in 3D FeNAND / Won-Tae Koo, Jihun Kim] 

In this work, SK hynix presents a holistic co‑optimization of 3D ferroelectric NAND (FeNAND) for energy‑efficient analog computation‑in‑memory. The co‑optimization simultaneously addresses cell properties, non-cell properties, and computational schemes. Our approach (1) enhances multi‑level capability by tuning the write algorithm, (2) reduces word‑line transition power, and (3) improves the efficiency of analog multiply‑and‑accumulate operations through in‑page pipelining and splitting. Consequently, the computational throughput and energy efficiency of 3D FeNAND are increased by up to 16× and 4950×, respectively, compared with emerging-memory based 2D arrays.