This article is based on the paper “A Highly Scalable Isolated Charge Trap Nitride Layer Implemented in a 176-layer 3D NAND Flash with Superior Threshold Voltage Distribution and Charge Retention” by Sangwan Jin et al., presented at IEDM 2025. The purpose of this article is to introduce and highlight the technological achievements of SK hynix for industry-wide awareness and contribution.

The aggressive scaling of stack height to enhance 3D NAND density has led to severe issues like high-aspect-ratio etching and wafer warpage. To overcome these challenges, the industry has adopted a strategy of reducing the tier pitch. However, this reduction has intensified cell-to-cell interference and degraded reliability, indicating that tier pitch scaling is now reaching its fundamental limit. To combat the increased cell-to-cell interference caused by aggressive tier pitch scaling, this work employs a Charge Trap Nitride Isolation (CTI) technique. While prior research has demonstrated CTI's effectiveness in low-stack test vehicles, practical solutions for high-layer 3D NAND have been absent. This work bridges that gap by presenting a novel CTI architecture, implemented and evaluated on a 176-layer test vehicle—the highest stack count reported in such studies.

The conventional CTI scheme formed a pocket to isolate the Charge Trap Nitride (CTN) by recessing the mold nitride. However, this approach had critical drawbacks for commercialization, including channel hole enlargement and significant process variation. In contrast, our novel technique forms the pocket on the inner side of the plug through a series of deposition processes, effectively preventing any increase in the channel hole size (Fig. 1). While direct comparative metrology data is limited, process experience and electrical results from 176-layer devices indicate this method achieves superior pocket uniformity.

 Fig 1. Schematic illustration of the CTI process flow, comparing the previously proposed scheme with the approach developed in this work.

To validate our CTI scheme, we compared our optimized CTI cells with conventional CTN cells across various CTN thicknesses. After TLC programming, CTI cells show a narrower threshold voltage (V_th) distribution and lower sensitivity to CTN thickness — thanks to 30% reduced Cell to Cell (CtC) interference. Across multiple wafers, CTI cells improve within-wafer V_th uniformity by 6.9% while matching conventional CTN Cell’s top-to-bottom consistency. At every program verify level and across all word lines, CTI cells consistently deliver tighter V_th distributions without compromising uniformity (Fig. 2).

Fig 2. (a) The experimental V_th distribution after TLC programming according to CTN thickness. (b) The within-wafer V_th distribution map and its box plot from CTI and NCTI wafers. (c) The typical V_th distribution of CTI and NCTI cells after TLC programming. (d) The V_th distribution according to WLs. (NCTI denotes conventional non-CTI cells)

Beyond reducing interference, the CTI structure enhances retention by replacing continuous CTN with spacer oxide — minimizing spacer holes that trigger electron spreading and blocking lateral charge paths between cells. TCAD simulations show that while CTN separation slightly increases vertical charge loss, the dramatic drop in lateral loss results in net retention improvement. Experimentally, after 12-hour baking at 125°C, CTI cells show 40% less V_th shift across all CTN thicknesses, with reduced thickness sensitivity confirming CTI’s effectiveness in suppressing lateral charge spread (Fig. 3).

Fig 3. (a) Charge retention mechanism of CTI and NCTI cells. (b) The TCAD prediction of charge loss of NCTI and CTI cells. (c) V_th shift from 125 °C, 12-hour baking retention of NCTI and CTI cells with respect to CTN thickness.

Using TCAD simulations, we projected how CtC interference, V_th distribution, and retention evolve under aggressive tier pitch scaling beyond NCTI’s limits. As tier pitch shrinks, NCTI cells show sharp rises in interference and V_th spread — while CTI drastically lowers both the absolute values and their sensitivity to scaling. This suggests a 4 nm tighter pitch is viable without degrading V_th uniformity. For retention, CTI enables scaling beyond 10 nm reduction, as shown in Fig. 4.

Fig 4. (a) CtC interference, (b) V_th distribution, (c) Retention widening as a function of tier pitch.

 In summary, we successfully implemented a highly scalable novel CTI structure in a 176-layer 3D NAND. Reduced CtC interference improved V_th distribution, enabling tighter tier pitches without degradation. Enhanced retention further supports scaling beyond current limits. High yield and uniform V_th across wafers confirm CTI’s manufacturability and scalability — making it a viable solution for next-generation 3D NAND scaling.

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