The motivation of this research is the evolution of conventional FE-RAM. HZO, the compound of hafnia and zirconia, is being studied as a material candidate for metal-ferroelectric-matal(MFM) capacitors. Especially, HZO has a low thermal budget and high step coverage. Through we combine HZO FE-Cap with DRAM cell array, we can manufacture high density, high performance, non-volatile memory.
We used PUND test method used for ferroelectric characterization. In U and D pulses, only dielectric charge and leakage current are measured, because polarity does not change. Ferroelectric switching current is measured in P and N pulses. We measure P-V curve using the ten thousand FE-Cap array test pattern. As the PUND voltage increases, two Pr increases significantly. Unlike general ferroelectric, you can see all four current peaks at 1.5 voltage measure.
Based on the TCAD simulation and actual measurement, we figure out a schematic diagram of the switching current of five nanometer-thick HZO. The center of P-V curve is not placed on zero Voltage, not symmetrical. This asymmetry is why we can use Anti Ferroelectric switching current from pinched hysteresis. If there is no asymmetry, there is no remnant polarization in low voltage operation. This asymmetry is due to the difference in the work function between the bottom and top electrode. The bottom TiN suffer oxidization during the HZO deposition process and has a lower work function than the top TiN. Due to this asymmetry, the polarization of anti-ferroelectric doesn’t disappear, and FE-RAM operation is possible using this remnant polarization. Similarly, a strategy to maximize 2Pr by maximizing asymmetry is also valid. However, the materials that can be deposited by ALD in 3D cap are limited. So, we propose asymmetric operation. While maintaining the overall voltage , in the positive direction, increases larger voltage, and the negative direction decreases the voltage, it would allow a larger switching green region to increase 2Pr.
In the results of evaluating asymmetric operation by adjusting Vcp at the chip level, you can see that the higher the Vcp, the higher the delV. This shows we can use asymmetric operation at the chip level.
In terms of domain wall propagation, the propagation rate slow down because it is disturbed by the defect. Therefore, it is necessary to properly control the defects.