In this work, we present the successful implementation of a novel charge trap nitride isolation (CTI) technology in a 176-layer production-scale 3D NAND device. In this approach, the charge trap nitride (CTN) layer is confined by a pocket with sidewalls formed through a deposition process, a first-time implementation that improves CTI scalability. We achieved sufficient process maturity to produce fully functional chips across a substantial wafer area, enabling chip-level evaluation of threshold voltage (Vth) distribution and retention. This technology achieves an 11% reduction in read time (tR), a 6.9% narrower Vth distribution width, and a 45% improvement in high-temperature retention after cycling compared to conventional continuous CTN cells. These results suggest the current tier pitch limit could be reduced by 4 nm in terms of Vth distribution and by more than 10 nm from a retention perspective, supporting our CTI technology as a compelling solution for continued 3D NAND scaling.