We presented this study at the IEEE Symposium on VLSI Technology & Circuits (VLSI 2024), which was held from June 16 to 20, 2024 in Honolulu, Hawaii, USA. This study received attention to SK hynix's global leadership in emerging memory technology and ecosystem revolution as a selection for the technology highlights session.

As the world rapidly develops into an AI and data-driven society, the memory hierarchy for high-performance computing systems is evolving. In particular, fast, high capacity and affordable storage-class memory (SCM) to address the storage bottleneck between current DRAM and SSD solutions will a new opportunity with the advent of CXL with flexible memory expansion. Fig.1 presents an exemplary schematic diagram of a data center memory solution in the near future. What is noteworthy here is the appearance of emerging memory SOM for CXL memory module (CMM). 

Fig.1 Exemplary schematic diagram of a data center memory solution in the near future and new memory hierarchy.

SOM is an ultimate cross-point memory device where a single thin film, known as a chalcogenide-based dual function material (DFM), can perform both functions of a selector and a memory. In this study, we report for the first time the characteristics of fully integrated 16 nm half-pitch SOM, demonstrating the new direction of cross-point memory scaling.

First of all, to investigate the origin of switching and conduction dynamics of SOM devices, the SOM was simulated by electro-/thermo- migration, ab initio and trap-limited conduction (TLC) model as shown in Fig.2

Fig. 2 SOM switching model and write-read flowchart of TCAD.

Fig.3(a) presents the optimized bi-polar core circuit scheme under a 16 nm half-pitch cell array for SOM. Fig.3(b, c) shows a cross-sectional TEM image of a part of the one-deck cell array with a peri under cell (PUC) architecture in array tile consists of WL 4 kb and BL 4 kb. 

Fig.3 (a) Bi-polar core circuit scheme for SOM. (b) Cross-sectional TEM image of 16 nm half-pitch cross-point SOM with PUC architecture and (c) SOM cell array.

Fig.4 (a) shows the Vt distribution of the 64 Mb array by applying a write pulse (30ns, 20uA) for both SET and RESET. To improve RWM (750 mV), we have optimized the novel DFM composition, treated the electrode interface, and developed effective sidewall passivation based on etch, cleaning, and ALD processes.

Fig.4 (a) SET / RESET Vt distribution of 64 Mb array. (b) Progress of RWM increment by advanced process integration.

We found that the main failure type in cycle endurance of SOM was the escape of DFM through the encapsulation layer interface. Therefore, we have developed the new DFM, electrode and encapsulation processes and have been especially devoted the treatment of cell's sidewall. Fig.5 shows the achievement of 10⁷ write cycles endurance under RBER 200 ppm.

Fig.5 Cycle endurance characteristics of measured RBER with write cycles.

In summary, we have successfully developed an optimized core architecture and novel process integration based on understanding of the theoretical mechanism of SOM. This study of the first fully integrated 16 nm half-pitch SOM demonstrates the scalability and performance advantages and presents its potential to be a promising solution for emerging CMM.

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