Recently, analog computation-in-memory (A-CiM) has been studied to improve energy efficiency of artificial intelligent (AI) computing. Since emerging non-volatile memories can offer analog dot-product in memory cell arrays, they can reduce data movements between AI accelerators and memories, improving energy efficiency of analog computations. As one of the potential candidates, HfO₂-based ferroelectric field-effect transistors (FeFETs) have been studied as a synaptic cell for A-CiM applications, due to their high speed operation, CMOS compatibility, and scalability. 

In this study, we developed a simulation framework for FeFET synapses by combining ferroelectric switching, FeFET threshold (Vth), and MOSFET models (Fig. 1). Then, we optimized analog properties of polycrystalline Si channel-based FeFET (poly-Si FeFET) devices using the FeFET synapse models. Lastly, we demonstrated the multi-level conductance states (≥ 16-level/cell) of poly-Si FeFET synapses and their improved power efficiency for A-CiM applications.

Fig. 1. Simulation model for FeFET synapses.

Firstly, we updated the FeFET synapse model using poly-Si FeFET devices (Fig. 2a), and simulated conductance values of FeFET devices as a function of write conditions. In general, multi-level states of FeFET devices for memory applications are mainly determined by gradual changes of FeFET ΔVth values. However, these gradual ΔVth changes of FeFETs can induce abrupt conductance changes (S1 and S3 in Fig. 2b and 2c, respectively). Therefore, we found the optimum write conditions to improve the analog properties of FeFETs, such as linearity and multi-leveling (S2 and S4 in Fig. 2b and 2c, respectively).

Fig. 2. (a) Experimental data of I_D-V_G curves of poly-Si FeFET devices with simulation results. (b) Simulation of conductance levels of FeFET devices under different PGM conditions: (b) V_PGM and (c) t_PGM scheme.

With the optimum write conditions, we modulated conductance states of poly-Si FeFET devices by sequential potentiation and depression pulses. The conductance of poly-Si FeFET devices was gradually increased by the potentiation steps and also gradually decreased by the depression (Fig. 3a), demonstrating the weight (conductance) modulations of poly-Si FeFET devices as a synaptic cells. Therefore, a single device of poly-Si FeFET synapses was tuned into multi-level conductance states (≥ 16 levels) with low current levels (Fig. 3b). The simulation for A-CiM applications revealed that the power efficiency of poly-Si FeFET synapses is 1.48-fold higher than that of bulk-Si FeFET devices (Fig. 3c), due to low current levels and multi-leveling properties.

Fig. 3. (a) Conductance values of the FeFET synapses in response to potentiation and depression pulses. (b) I_D-V_D curves of FeFET synapses with various conductance levels. Simulation of FeFET synapse-based A-CiM performances. Simulation was conducted by using NeuroSim (X. Peng et al., IEEE IEDM, 2019). 

In summary, we modeled the multi-level weight conductance states in FeFET devices, and confirmed the multi-leveling properties of poly-Si FeFET synapses with low current operations improve the energy efficiency of analog computations. Our results demonstrated that FeFET synapses can be an energy efficient platform for A-CiM applications.

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