This study was presented at the 2025 IEEE Symposium on VLSI Technology and Circuits (VLSI 2025), held June 8–12, 2025, in Kyoto, Japan. Selector-only memory (SOM) has emerged as one of the most promising storage-class memory (SCM) candidates beyond 3D XPoint, offering clear advantages in scalability, process complexity, and latency. With latency shorter than 100 ns and excellent endurance characteristics, SOM holds significant potential for applications in compute express link (CXL) environments. To achieve near-DRAM performance, endurance exceeding 107 cycles is critical for SCM.

In this study, we successfully integrated a 16 nm half-pitch SOM with a two-deck architecture, configured into a 4k × 4k array mat. Through process, structure, and design approaches, we achieved endurance exceeding 107 cycles, effectively addressing key challenges associated with large-scale SOM arrays and their integration.

 

Fig. 1(a) and (b) shows TEM images of a two-deck 16 nm half-pitch SOM cell array, with the 1st and 2nd decks sharing a common BL and identical cell structures. Robust read window margin (RWM) characteristics for both decks, with no degradation observed in the tail properties of the SET/RESET distribution, are demonstrated in Fig. 1(c).

 

Fig. 1. (a) Cross-sectional TEM image of a 16 nm half-pitch, two-deck cross-point SOM featuring PUC architecture. (b) Array of two-deck SOM cells. (c) SET/RESET Vth distributions in 1st deck and 2nd deck SOM arrays.

 

Fig. 2(a) shows the cycling endurance trend of our dual-functional material (DFM) system with varying As concentration. DFT simulations suggest that increased As content reduces atomic mobility and stabilizes the amorphous structure, enhancing endurance. Based on this, we optimized the As concentration to balance endurance and electrical performance. We also found that oxidation-induced encapsulation deformation degrades endurance. To prevent this, we developed an enhanced encapsulation process (EEP), which improved endurance by a factor of 2.47, as shown in Fig. 2(b). Further process optimizations—including refined etch conditions, improved array encapsulation, and DFM composition tuning—yielded additional endurance gains, as shown in Fig. 2(c).

 

Fig. 2. (a) Endurance characteristics as a function of As concentration in DFM. (b) Cycle vs. RBER showing improved endurance with enhanced encapsulation compared to the normal encapsulation process. (c) Endurance improvement relative to the base condition for S1, S2, S3, S4, and S5.

 

To suppress the spike current in the zone NEAR, we optimized the cell stack resistance. As shown in Fig. 3(a), our cell stack incorporates electrodes and resistance layers (RLs) capable of providing additional resistance. Notably, the RL exhibited up to approximately a 7-fold change in resistivity depending on the process conditions (Fig. 3(b)), with additional tunability achieved through thickness adjustment (Fig. 3(c)).

 

Fig. 3. (a) Electrode and resistance layers for cell stack resistance. (b) Resistivity of the resistance layer (RL) as a function of process conditions. (c) Resistance as a function of RL thickness.

 

We implemented a local X switch gate voltage (VLXG) control scheme to suppress spike current in the zone NEAR during write/read operations (Fig. 4(a)). Additionally, SOM Vth scaling reduced operating voltage, lowering spike charge and improving power efficiency (Fig. 4(b)). As a result, 2R1W power consumption was reduced by 47% in Stage 2 compared to Stage 1 (Fig. 4(c)).

 

Fig. 4. (a) Time vs. cell current as a function of VLXG, simulated for the zone NEAR. (b) Reduction in operating voltage achieved through Vth scaling of SOM. (c) Comparison of two read, one write (2R1W) power consumption between Stage 1 and Stage 2.

 

Fig. 5 summarizes the key factors and processes that contribute to achieving endurance characteristics exceeding 107 cycles. In summary, this study successfully demonstrated, for the first time, a 16 nm half-pitch SOM with a two-deck architecture, achieving endurance beyond 107 cycles. The approaches employed here are expected to play a significant role in establishing SOM as a robust candidate for emerging SCM applications.

 

Fig. 5. Cycle vs. RBER showing endurance improvements from different factors.

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