[Summary] Demonstration of Ultra-thin Ferroelectric/dielectric and Anti-ferroelectric/dielectric Bilayers for Future DRAM Cell Capacitors
One of the critical challenges as DRAM cell scaling continues is that DRAM cell capacitances are decreased In order to meet criteria for future DRAM cell capacitors, it is imperative to develop dielectric materials having a higher dielectric constant (k) in an ultra-thin physical thickness (< 6 nm) with low leakage currents.
In this study, we optimized ultra-thin ferroelectric (FE)/dielectric (DE) and anti-ferroelectric (AFE)/DE bilayers for applications in DRAM cell capacitors (Fig. 1). We further demonstrated their real operation in 1T1C DRAM cells in 12-inch wafers using the state-of-the-art 1X nm DRAM technology.

Fig. 1. (a) TEM image of pillar-type capacitor arrays. TEM images of (b) o-phase rich and (c) t-phase rich HZO thin-films. (d) Schematic illustration of FE/DE and AFE/DE capacitors.
We controlled the capacitance ratios of FE/DE (C[FE]/C[DE]) and AFE/DE (C[AFE]/C[DE]) bilayers to optimize electrical properties, in terms of equivalent oxide thickness (EOT) and remnant charges (Qrem) at 0.6 V. The decrease in the EOT of FE/DE capacitors is accompanied with the rapid increase in Qrem. On the other hand, the AFE/DE capacitors exhibited very slow increase in Qrem as decreasing EOT values, due to the small Qrem and higher Vc of AFE-like t-phase HZO than those of FE o-phase HZO.

Fig. 2. Qrem and EOT as a function of (a,b) C[FE]/C[DE] and (c,d) C[AFE]/C[DE]. (e) Trend of normalized Qrem and EOT for various capacitors.
In addition, we demonstrated 1X nm DRAM operations of AFE/DE and FE/DE capacitors using a typical DRAM write recovery time (tWR) evaluation method at hot (95°C) and cold (–10°C) temperature (Fig. 3). Even though the capacitors have similar BV and EOT values, the AFE/DE capacitors showed significantly fewer write failures than the FE/DE capacitors. This tendency is because large amounts of Qrem in the FE/DE capacitors acts as opposite polarities during write operation and hinders subsequent DRAM operations.

Fig. 3. DRAM tWR results at (a-c) 95℃ and (d-f) –10℃. (a,d) Scatter plots for fail bits, (b,e) Normalized Qrem versus tWR, and (c,f) 12-inch wafer maps for fail bits.
In summary, we investigated the electrical properties of FE/DE and AFE/DE bilayers as a function of capacitance ratios, and demonstrated their real operation in 1X nm DRAM cells. Our study revealed that the strict control of Qrem is necessary to stable DRAM operations, thereby indicating that AFE/DE layers are more favorable than FE/DE layers for use as DRAM cell capacitors.
The publication: Link


![[Summary] A Memristor-based In-Memory Computing SoC with Efficient Depthwise Convolution](https://mis-prod-koce-research-user-cdn-01-blob-ep.azureedge.net/web/blog/20260806/thumb_sEVmfv3K.20260806085519833.jpg)
![[Insights] Evolving Role of Emerging Memories in Next-Generation Computing](https://mis-prod-koce-research-user-cdn-01-blob-ep.azureedge.net/web/blog/20260806/thumb_NgJoNLYn.20260806080458980.jpg)
![[Summary] Electrical Characteristics of the 4F2 Vertical Gate (VG) DRAM integrated with Bit-Line Shielding (BLS) and Back Gate (BG) Transistor](https://mis-prod-koce-research-user-cdn-01-blob-ep.azureedge.net/web/blog/20260806/thumb_DOUurl5m.20260806080624234.png)