STT-MRAM has been in the spotlight for embedded memory applications owing to the versatility of performance in terms of fast operation speed (<10 ns), high data retention (>10 years at 85~150℃), and high endurance (>1E10).  However, it has been challenging to enter into high-density memory applications because stand-alone MRAM has struggled to enter big-volume market due to lack of cost competitiveness. A cross-point structure of 4F² feature dimension can expand STT-MRAM application to low-cost and high-density memory such as storage class memory (SCM) when combining a selector having high current drivability.

Fig. 1. (Left) Schematics of cross-point MRAM array, (Right) Cross-sectional view of full integration of 45 nm pitch 1S1M array architecture.

At the IEDM 2022, we shared the results of the fabrication of 1 selector-1 MTJ (1S1M) cells and array integrated in 45 nm of cell pitch and 20nm of MTJ diameter on CMOS circuit. The prior research and development of the unit devices such as As-doped SiO₂ selector and MTJ has been conducted, and then co-optimizing As-doped SiO₂ process compatible to MTJ stack and 1S1M patterning for pitch reduction allowed to realize 1S1M array operation with 2 Kb macro.

Fig. 2. Electrical characteristics of the unit MTJ (Left) and selector devices (Middle). Read-out signal of 1S1M array is verified and improved for 2Kb macro (Right). 

It is well known that the electrical properties of MTJ easily degrade by reducing not only MTJ diameter but also the space between MTJs. We obtained almost equivalent RV characteristics of MTJ even scaling down by optimizing MTJ stack and patterning process. In addition, high performance selector devices having low threshold voltage, low half-selected cell’s leakage current, and low snap-back voltage are acquired by engineering implantation dose of As dopants, thickness of SiO₂, and middle electrode materials. Finally, the read-out signal (ΔV_out) of 1S1M array is proven to be legitimately dependent of MR of MTJ, and it could be enhanced when further improvement of processes is conducted.

Fig. 3. Comparison of physical scale of various STT-MRAM technologies. High density MRAM array demonstration based on 1T1M with 9F² feature dimension (2016 IEDM by SK hynix-Toshiba), and 1S1M with 4F² cross-point architecture (2022 IEDM by SK hynix-Kioxia). 

For the first time we successfully demonstrated the excellent performance of 1S1M cells integrated in cross-point array structure with the world smallest both of cell pitch (45 nm) and MTJ diameter (20 nm) at the same time. We believe that the continuous challenging toward high density STT-MRAM technology will pave the way for the potential of high density STT-MRAM. 

The publication: Link