CXL(Compute Express Link) has emerged for efficient connection between the various components in terms of power and resources. In CXL environment, memory is required for optimizing performance and capacity. Today, we will introduce the new class of memory, SOM (selector-only-memory or SSM(self selecting memory)) which is suitable for CXL memory in the AI era. 

Since the commercialization of the 3DXP, it has been attention as its high capacity, low latency, and byte-addressability. Although the 3DXP can provide high capacity with its 4F² footprint and 2z nm scale feature size, however, it is expected that further scaling will face the limit. In terms of integration, since 3DXP cell stack consists of a thick PCM, an OTS, and many electrodes, it results in a very high AR. In addition, PCM and OTS are floppy chalcogenides of which 20-30% of the volume are void or defect, such a leaning or wiggling phenomenon will appear easily. In addition, performance-wise, PCM’s melting process driven thermal disturbance (TDB) will hinder the scaling of the 3DXP due to the smaller spaces between the cells. 

At the IEDM 2022, we shared the excellent performances of array operation of 20 nm self-selecting memory (SSM) for the first time. SSM has a single cell stack which acts as both memory and selector in bi-directional operations. The single cell stack consists of a cell material (dual function material), two electrodes, and two metal lines. Due to this simple stack, it can overcome the scaling limit of conventional PCRAM.

Fig. 1 (Left) Cross section TEM of SSM cell stack (Right) the plan-view SEM of 8 Mats making up a 32Mb array

It is well known that chalcogenide material based device has large distribution. Read window margin (RWM), the main hurdle for high density array operation, was successfully obtained by cell stack materials engineering with the help of bipolar write operations. Sufficient RWM can be obtained even below a write pulse of 20 ns for both Set and Reset, and at a much lower write current than the conventional 3DXP, which guarantees extremely low write latency and power consumption. Owing to the low write current and short write pulse, it is expected that the operation stresses of SSM are much weaker than those of 3DXP. Therefore, SSM also displayed superior write cycle endurance up to 1E7cycle. 

Fig. 2 Innovative cell stack engineering, including materials development, made it possible to increase the RWM considerably and finally achieved a larger RWM than 3DXP.

The fundamental operation mechanism of SSM is thought to be related to atomic migration model. The vertical composition distribution of DFM Cell detected by EDS. Obvious differences are detected in three major elements, when Set and Reset bias are applied in opposite directions. More atomic migrations are detected, when the atoms have more electro-negativity. However, the atomic migration model with conventional transport theory cannot explain the V_t difference. A theoretical explanation will be further studied.

Fig. 3 The vertical composition distribution of DFM Cell detected by EDS

Due to the elimination of phase change material (PCM), SSM showed no write disturbance (thermal disturbance), and this can improve the total system power consumption and performance as well. In addition, the changes of cell characteristics caused by scaling is expected to be smaller. In practice, when we make cell CD reduction from 18nm to 15nm in the same pitch, the change of V_t is quite small. SSM is expected to have more scalability

Fig. 4 Comparison table of 3DXP and SSM

We demonstrated the successful array operation of SSM at 20 nm technode for high density memory applications as a successor of 3DXP. SSM outperforms 3DXP in terms of write latency, cell power consumption, and reliability. The lower AR seems promising for the scaling of technode below 1z nm. SSM’s excellent latency and low power consumption may be able to make up for the deficiency of 3DXP for CXL memory in the future. SK hynix believes that SSM can also be extended to vertical SOM, which is reported by S. Yoo at the 2022 IEEE International Memory Workshop.

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