The Von Neumann architecture is deeply embedded in our lives, thanks to its robust, practical, and economical mode of operation. This computing method is composed of distinct components responsible for logic and memory, and has continuously evolved to ensure synchronization between these parts and to enhance their individual performance. The fundamental reason for this drive for improved performance is the exponential increase in the amount of data that needs processing. Therefore, the key direction for the development of materials, devices, and systems related to computing is to enable data processing with minimal energy consumption and high speed.

More specifically, in the Von Neumann architecture, the central processing unit (CPU) responsible for logic sits at the top in terms of processing speed, with various types of memory arranged in a hierarchical structure beneath it. SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory) are known for their volatility (losing stored information when power is off) and high speed, while NAND Flash is known for its non-volatility and relatively slower speed. This memory hierarchy is optimized according to the operational characteristics of each type, and they process data through close communication with the CPU. From the past to the present, and likely for some time to come, this memory hierarchy is expected to handle data processing without major issues.

However, to improve the overall performance of the system, the memory hierarchy is becoming more segmented. This direction of development may have disadvantages in the long term, as data movement between layers could hinder low-power and high-speed operation. Nevertheless, the reason memory devices have been layered in this way is that there was no single memory device capable of offering both high speed and non-volatility.

Over the past 20 years, various next-generation non-volatile memory devices, such as RRAM (Resistive Switching RAM), PRAM (Phase Change RAM), and MRAM (Magnetic RAM), have been developed with the aim of either replacing traditional memories like DRAM and NAND Flash, bridging the gap between them, or supporting their performance. However, these devices have not shown significant success. Several issues contribute to this, including operational reliability (e.g., endurance—how many times the memory can be written and erased, and retention—how long the data remains unchanged after being written) and operational variability.

Recently, led by companies like SK Hynix and Samsung Electronics, a new type of memory device called Selector-Only-Memory (SOM) has been proposed. The name comes from the "selector" element, which was previously inserted as an auxiliary component to ensure stable operation of next-generation memories. In SOM, this selector not only stores information but also performs the selection function simultaneously, allowing it to take a leading role in memory operations. This is expected to result in advantages such as reduced aspect ratio required for high-density memory devices, lower standby power, and improved operational speed. However, challenges remain, such as developing optimized materials for SOM, establishing unit processes for these materials, developing Atomic Layer Deposition (ALD) processes for vertical devices, securing a memory operation window, and suppressing voltage drift during operation.

Research on SOM is still in its early stages globally. There is room for both industry and academia to lead relevant research, and I believe that close collaboration between the two will solve the challenges presented. Alongside Von Neumann architecture computing, semiconductor memory devices will also become increasingly important in brain-inspired computing, which is designed for the efficient processing of new, unstructured data. I hope that researchers will continue their efforts to maintain South Korea's status as a leading country in semiconductor memory, with SOM being one of the key candidates in this pursuit.